1. Field of the Invention
The present invention relates to a DSRC (Dedicated Short Range Communication) communication circuit and communication method for use in DSRC wireless systems.
2. Description of Related Art
ETC (Electronic Toll Collection) systems, incorporated today in ITS (Intelligent Transport Systems), employ DSRC wireless systems that comply with the standard ARIB-STD-T55. In DSRC wireless systems, a transmission frame is formed with a plurality of slots of an equal width so as to enable TDMA (Time Division Multiple Access) methods of synchronization control. In addition, the standard ARIB-STD-T75, issued recently, proposes a DSRC communication system that changes the modulation method per slot in a frame.
A typical timing generation method employed in a DSRC communication circuit used in conventional DSRC wireless systems uses one bit counter and slot-synchronizes this bit counter at the unique word detection timing in each received slot and generates, from the count value in the slot-synchronized bit counter, the operation timings of received data (the operations including the CRC operation and simplified privacy scrambling), the data reception timing for taking the received data after the operations into a reception buffer, the timing of the unique word detection window in the next received slot, the data transmission timing, and the operation timings of transmission data (the operations including CRC operation and simplified privacy scrambling). See, for example only, Unexamined Japanese Patent Application Publication No. HEI09-289499.
However, conventional timing generation methods such as the one described above have at least the following problems. That is, in terms of data reception, slot synchronization is performed utilizing the unique word detection timing in the received slot, and the timing of the next unique word detection window is generated. Consequently, when the slot timing deviates from the frame timing, the unique word detection timing in the corresponding received slot will also deviate, and the gap between the frame timing and the slot timing will show in the timing of the unique word detection window in the next received slot.
So, when one frame of data communication is over and data reception in the fist slot of the following frame is performed, despite the fact that the relationship (gap) between the frame timing and the slot timing changes when the frame changes, the unique word detection window in the following frame is generated showing the gap between the frame timing and the slot timing in the previous frame. As a result, the timing of the received data and the timing of the unique word detection window do not match, causing a unique word detection error and eventually leading to the problem that processing such as waiting for data retransmission and continuous unique word reception need to be performed.
In addition, in terms of data transmission, as in data reception, slot synchronization is performed based on the unique word detection timing in the received slot using one bit counter, and the data transmission timing and the operation timing of transmission data are generated from the count value in the slot-synchronized bit counter. Consequently, when the slot timing deviates from the frame timing, the timing of slot synchronization will also deviate from the frame timing, and, as a result, the data transmission timing and transmission data operation timing will be generated in timings that deviate from the frame timing.
Now, to offer a solution to the resulting problem of incompatibility and communication errors between vehicles of various manufacturers mounting DSRC systems and roadside equipment, it is necessary to be able to perform data transmission in synch with the frame timing. Still, conventionally, it is not possible to perform data transmission in synch with the frame timing, and so improvement is desired.